This invention relates to an improved circuit for converting a balanced logical signal of one polarity into a logical signal of the opposite polarity.
When a digital circuit is implemented using bipolar transistors and emitter-coupled logic (ECL), logical zero is represented by two different negative potential levels (typically -1.8 volts and -0.65 volts) carried on first and second conductors, whereas logical one is represented by these same potential levels on the second and first conductors respectively. When a digital circuit is implemented using complementary metal-oxide-semiconductor (CMOS) technology, logical zero and logical one are represented by two different positive potential levels, respectively below and above a threshold of 2.5 volts. Typically, logical zero and logical one are represented by 2 volts and 3 volts respectively, and the maximum range is from 0 volts to +5 volts.
The ECL system is superior to the CMOS system for transmission of signals over long distances, because the ECL system generates less electromagnetic interference than the TTL system and requires less power to drive a terminated transmission line. (It will be understood that what constitutes a long distance depends on the frequency involved: at gigahertz frequencies, 0.5 cm is a long distance.) On the other hand, a higher level of integration can be achieved with CMOS technology than with circuits that operate in the ECL system. Accordingly, a need exists for a circuit that is capable of converting an ECL logical signal having ECL voltage levels to CMOS voltage levels, so that CMOS components can be used in conjunction with an ECL transmission system.
A known circuit for converting a balanced logical signal of one polarity to a single-ended logical signal of the opposite polarity is disclosed in U.S. Pat. No. 4,536,665 (Dayton). This circuit is shown in FIG. 1 of the accompanying drawings, and its operation is fully described in U.S. Pat. No. 4,536,665.
The circuit disclosed in U.S. Pat. No. 4,536,665 may be used as an ECL to CMOS converter, but it is subject to some disadvantages. When the input signal changes from logical one (P1 at -0.65 volts and P2 at -1.8 volts) to logical zero, the potential on output conductor P3 initially drops rapidly to a slightly positive voltage (one base-emitter drop minus one Schottky break above ground). However, the potential on conductor P3 then continues to fall, albeit at a reduced rate, as the base-collector capacitance of transistor Q4 and the load capacitance from conductor P3 to ground are charged through resistor R2, so that the final potential level of conductor P3 is about one Schottky break below ground. Further, the increase in the effective base-collector capacitance of transistor Q2 due to the Miller effect lowers the input impedance of transistor Q2 so that the circuit does not have a balanced input impedance. When transistor Q1 is on, its collector is held at a substantially constant level by virtue of the fact that it is connected to the base of transistor Q3, which is connected as a common emitter amplifier. On the other hand, when transistor Q2 is on its collector voltage varies quite widely because the collector of transistor Q2 is connected through resistor R2 to the collector of transistor Q3. As a result, the circuit of FIG. 1 causes differential mode to common mode translation.